1. Field of the Invention
This invention relates to the manufacture of semiconductor devices. More specifically, it relates to semiconductor devices containing fuses that are disposed in a compact interconnect structure and methods for disconnecting them.
2. Background of the Related Art
Custom electronic devices that are made from standard components suffer from several disadvantages. Since several components are required to implement such a custom device, more circuit board space is required than if a custom or semi-custom integrated circuit had been used in place of the standard components. This makes the overall size of the device larger and more expensive. Also, the assembly process is longer, more costly, and prone to reworks or scrap, since more components are used. Further, a larger number of components usually require more power consumption, which means a larger, heavier, and more expensive power supply. Therefore, the overall size, weight, and cost of the resulting custom device may make it unappealing to the consumer or not competitive when compared to a similar product offered by another company. Accordingly, custom or application-specific integrated circuits (ASICs) are frequently used to implement new circuit designs in the place of standard components.
There are several types of ASICs which are available, depending on size, power, and programmability requirements, and volume of devices used. Fully custom devices offer the lowest cost and least amount of power consumption, but are only economical in very large quantities because of the costs of a custom mask set and engineering design time. Semi-custom devices such as gate arrays require a smaller number of custom masks and design time as compared to fully custom devices, but have a larger die size, cost more to produce, and are typically used when needed quantities are not quite as large. Similarities exist in custom and semi-custom devices in that both have relatively long lead times to produce prototypes and production volumes, and the designs are expensive and time consuming to change. Since the non-recurring costs are so large, it is not economical to produce them in small quantities. Other non-custom devices, such as programmable array logic (PALs), field-programmable gate arrays (FPGAs), and programmable logic devices (PLDs), are fabricated as unprogrammed xe2x80x9cblanksxe2x80x9d which are programmed by the end user as packaged units or after installation onto a circuit board. These non custom devices have a lower cost basis for smaller quantities, since no custom masks are required. The lead time to produce prototypes and production quantities is short, since the programming is performed near the end of the manufacturing cycle. They are also useful for designs that are expected to undergo revisions, since virtually no programmed material needs to be inventoried. However, these non-custom devices have the drawback of requiring a relatively large amount of die area dedicated to circuitry to perform the programming, and to signal paths to provide flexibility in routing. They are, therefore, more expensive to fabricate and don""t achieve the same programmable capacity as custom devices and gate arrays. In some cases, they also use more power and are slower.
Programming of the non custom programmable devices is sometimes accomplished through the use of disconnectable fuses. In this specification, the word fuse will be used to refer to fuses, anti-fuses, disconnection points, disconnectable links, or any combination of these terms. In certain types of programmable devices using electrically disconnectable or connectable fuses, the fuses in the device which define how the circuit is configured are accessed through the I/O pins on the device package. For techniques which require joining conductive regions together (for example, shorting a P/N junction), an excessive amount of current relative to normal operating conditions is passed through the junction, shorting it and allowing current to pass freely. To disconnect a conductive line, a fuse element in an undesired conduction path is subjected to enough current to heat it to its melting point, causing structural breakdown and creating a disconnection. Both of these methods require a relatively large amount of current to program the device. The transistors for generating these large currents in conventional MOS devices require large channel widths. Furthermore, a certain amount of heat insulation area is required around the fuses to prevent thermal damage to neighboring circuitry. This makes it difficult to achieve high device packing densities using these programming methods. Other devices have fuses that are disconnected through the use of a laser or other radiant energy beam device (hereinafter referred to as a xe2x80x9claserxe2x80x9d). For these devices, the laser is used to disconnect the fuses near the end of or after the conclusion of the fabrication process. These laser programmable devices have a smaller die size than the electrically programmable devices, and don""t require expensive precision custom masks and long lead times like the custom and semi-custom devices. The laser programmable devices are also economical to produce in smaller quantities compared to custom devices.
In addition to using fuses for the customization of an integrated circuit to give it specific circuit or electrical characteristics, fuses have also been used to (1) repair non-functional devices through the selective deletion of defective portions of the circuitry, or by substituting functional redundant circuitry for the defective portions of the circuitry; and (2) mark the device for identification of characteristics in a manner that is readable visually or electrically, for example serialization of the integrated circuit, or how the device has been configured by the laser.
FIG. 1 shows an array of fuses that can be disconnected by a laser. Fuse body 2 on fuse 1 is irradiated by laser beam 7, which has an energy distribution that is approximately radial Gaussian in nature. This energy distribution results in an effective laser spot size 6, that is the area of the beam that has an energy sufficient to disrupt active circuit elements. This disruption can be physical damage that causes the device to be non-functional, or it could cause performance degradation, such as silicon crystal dislocation that causes current leakage. The two characteristics that define the area requirements for a fuse, also called the fuse cell, are the pitch of the fuses in a group, and the length of the fuse. These two dimensions have a direct bearing on how much die area the fuse cell occupies, and thus the overall die size. The pitch 5 of the fuse cell is the distance from the center of one fuse to the center of the nearest neighboring fuse. This dimension is controlled by the requirement that the spot size 6 not disrupt any other fuses, and is conventionally calculated by adding the diameter of the spot size 6 and two times the maximum expected alignment error in the placement of the spot. The length 8 of the fuse is the sum of the length of fuse body 2 and fuse terminals 3. The length 8 of the fuse 1 is controlled by the need to isolate the thermal energy transmitted to the fuse by the laser from interconnect lines 4 attached to the fuse. Another influence to the area requirements of the fuse is whether circuitry can be routed underneath or in close proximity to the fuse. Most design rules specify that all of the area underneath of the fuse, and a certain area around it, be free of active circuitry to protect it from damage. Some designs provide for a barrier at another level between the fuses and the active circuitry and thus utilize some of the area.
As is also well known in the prior art, laser type fuses can alternatively be disconnectable by photolithographic techniques combined with etching to remove a section of the fuse, thus forming a disconnection. Photoresist layer 21 in FIG. 2 is patterned to make a hole 22 in the photoresist over the fuse 24. Well-known etching techniques are then used to etch through the fuse 24, completing the disconnection. As can be seen from FIG. 2, the disconnection can be made cleanly and thoroughly without a risk of damage to any underlying circuitry 25, which would not typically be routed under the fuse, but is shown here to illustrate that such routing can take place if desired.
FIG. 3 illustrates that a smaller disconnection hole 31 on fuse 32 permits a smaller pitch 5. Since the thermal isolation requirements are not needed when using photolithographic techniques, the length of the fuse can also be shortened. The above-mentioned methods of disconnecting fuses can be used, in varying degrees, to reduce required fuse cell area and thus permit a smaller fuse cell and an advantageously smaller die.
An example of the fuse structure from FIG. 1 that is designed with rules optimized for a masking process is shown in FIG. 4. Although the fuse layer in FIGS. 1 and 4 is shown to have an interconnection layer patterned on a layer above it, it should be apparent to one skilled in the art that the fuse layer could be formed as the lop level layer with the interconnect layer at some level below it. The fuse pitch 41 is no longer defined by a laser spot size, but by the minimum spacing 42 between features for the fuse layer 43, as well as the minimum connection pad dimension 44. Since the thermal isolation requirements are not needed when using a masking process, the length 45 of fuse 46 is defined by the minimum linewidth for the fuse layer 47 plus the expected registration and sizing errors of the disconnect hole 48. All of these changes in fuse structure requirements permit a smaller fuse area resulting in an advantageously smaller die. For comparative purposes, the area required for the fuse structure shown in FIG. 1 is the product of dimension 9 (drawn at 16.8 xcexcm) and dimension 10 (drawn at 14.0 xcexcm) for a total area of 235.2 xcexcm2. The area required for the fuse structure shown in FIG. 4 is the product of dimension 49 (equivalent to dimension 9 and drawn at 12.6 xcexcm) and dimension 50 (equivalent to dimension 10 and drawn at 8.4 xcexcm) for a total area of 105.8 xcexcm2.
A further reduction in the area required for a fuse structure can be realized by making use of a vertical fuse at the connection point between two interconnect lines. FIG. 5a shows a top view of the fuse structure from FIG. 1 and FIG. 4 that is designed using vertical fuses. The cross-section of FIG. 5b is taken along the line B-Bxe2x80x2 from FIG. 5a. An insulating material such as doped or undoped silicon dioxide 51 is formed over first interconnect layer 52 and patterned to form a plurality of vias 53. A filler material for vias 53, such as tungsten plug 54, is used to fill vias 53 and provide a connection to a second interconnect layer 55. A disconnectable conduction path is thus formed between the first interconnect layer 52 and the second interconnect layer 55 through plug 54. At the time that the circuit is ready for customization or repair, a photoresist layer 56 is applied and patterned with disconnect hole 61, and a core section of material 62 is removed using etching techniques, forming a disconnection 63 as shown in FIG. 5c. 
The length 57 of the fuse structure is defined by the minimum spacing 58 between features on the second interconnect layer 55, and the minimum connection pad dimension 59. The width of the fuse structure 60 is defined by the minimum connection pad dimension 59. For comparative purposes to the fuse structures shown in FIG. 1 and FIG. 4, the area required for the fuse structure shown in FIG. 5a is the product of dimension 57 (drawn at 17.4 xcexcm) and dimension 60 (drawn at 3.0 xcexcm) for a total area of 52.2 xcexcm2.
While the vertical fuse structure shown in FIGS. 5a-5c requires the smallest amount of area to implement, it suffers from some disadvantages. The disconnect hole 61 must be small and precisely positioned, requiring the use of expensive precision lithography equipment, precision masks for each design, and the use of more expensive lithography materials and processes, incurring a relatively high manufacturing cost for the device. If the disconnect hole 61 is too large, or misplaced such that it overlaps the vertical fuse structure 64 creating gaps 65 as shown in FIG. 6, the etch processes required to remove the vertical fuse structure 64 and customize the circuit can damage the first interconnect layer 52, as shown in FIG. 7. An alternative to the precision lithography processing would be to deposit insulating layer 67 after customization, since less etching would be required and the risk of damage to the first interconnect layer 52 would be minimized. However, insulating layer 67 is required to prevent corrosion of the sidewalls of second interconnect layer 55 during storage of the unconfigured circuits, so this processing sequence would not permit material to be stored for later customization, requiring a significant amount of planning to avoid shortfalls of material or scraps because it was not used before being damaged by corrosion. Another alternative would be to increase the top surface dimension of second interconnect layer 55, so that such dimension is at least as large as that of the disconnect hole 61, but this results in an undesirable increase in the die size. Still another alternative would be to avoid routing circuitry under the fuse structure 64, but this also results in an undesirable increase in the die size.
It is therefore desirable to have a structure and method for customizing a device using a vertical fuse without the need for precision masking equipment and processes, that permits the deposition of a protective layer over the vertical fuse structure, while allowing for the use of active circuitry below such a vertical fuse, and without increasing the dimensions of the second interconnect lines, thereby maintaining an efficient layout of the circuitry and a small die size while reducing processing costs.
It is an object of this invention to decrease the amount of space required for a disconnectable link, or an array of disconnectable links which form a specific circuit such as an AND array, thus reducing the overall size of the integrated circuit, without the need for precision photolithography at the customization step.
It is another object of the present invention to provide a fuse structure and a method of disconnecting a fuse that allows for active circuitry to be disposed below the fuses and not damaged during fuse disconnection.
It is another object of this invention to reduce the cost of manufacturing an integrated circuit by permitting the use of non-precision photolithography techniques to perform the customization.
In one embodiment of the invention, after manufacture of a disconnect fuse circuit, windows are opened in the insulating film overlying the second interconnect layer at all possible disconnection points, the disconnection points preferably being an exposure window that is aligned over a disconnect fuse circuit that includes a via that electrically connects electrical conductors disposed on different respective layers. This insulating film may consist of one or more layers of one or more materials, but preferentially consists of a single layer of silicon oxide. The wafer is then stored for later configuration. When the wafer is to be configured, a non-precision mask is manufactured. The wafer is coated with photoresist and patterned using the mask to produce disconnection holes in the photoresist at the desired disconnection points. Since the area over the desired disconnection points are free of the insulating film overlying the second patterned interconnect layer, the etching process can be limited to etch techniques which are optimized to etch metal with selectivity to the insulating film. The areas at the disconnection sites that are covered by the insulating film are further protected during the etch process, since the insulating film acts as an etch barrier to inhibit the etching of active circuit elements in proximity to the desired disconnect points.
The invention also allows an additional film or films to be deposited on top of the insulating layer. This film is selected to have properties wherein it will have a high level of selectivity to the metal etch process, and will thus function as a more effective etch barrier than the insulating layer alone.
Furthermore, the invention allows for the insulating layer to be formed using planarization techniques, such that it provides a thicker layer of insulating material over the active circuit elements to be protected, thus providing a more effective etch barrier.